PDS Tech is currently recruiting for a Electrical Engineer 3 in Baltimore, MD!
Job Title: Electrical Engineer – Principal or Sr. Principal Custom IC Layout Engineer
Job Type: Full Time, Consultant (6 Months)
Location: Baltimore, MD 21240 (Hybrid with on-site requirements in Morrisville, NC; Rolling Meadows, IL; or Baltimore, MD)
Schedule: Monday to Friday, 5x8 Hybrid
Pay Rate: $47.79 to $60.51 per hour
Position Overview
PDS Tech is actively seeking a highly skilled Electrical Engineer- Principal or Sr. Principal Custom IC Layout Engineer for our Hardware Synergy Electrical Design and Integrated Circuit (EDIC) team. This role offers a unique opportunity to work within our semiconductor foundry, focusing on the design, manufacture, and testing of semiconductor products for both commercial and emerging programs. For the right candidate, hybrid or remote work options may be available, with on-site attendance as required.
Responsibilities
Develop and verify hierarchical mixed-signal chip and circuit layouts, including ADCs, DACs, PLLs, band gaps, and voltage regulators.
Utilize Cadence Virtuoso XL, ensuring quality layouts at all levels of hierarchy, including chip-level.
Interpret results from layout verification tools such as Calibre DRC/LVS or Cadence Assura/PVS.
Generate, review, and analyze top-down floor plans for accuracy and efficiency.
Create staffing plans, task schedules, and deliver verified layouts on time.
Participate in reticle composition and support tape-out activities.
Develop and document reusable workflows for layout tasks to ensure quality and efficiency.
Basic Qualifications
Clearance: Must be eligible to obtain a U.S. Department of Defense Security Clearance.
Experience:
Principal Level: Associate’s degree in a relevant field with 8 years of experience, or Bachelor’s degree with 5 years of experience.
Sr. Principal Level: Associate’s degree with 12 years of experience, or Bachelor’s degree with 9 years of experience.
Proficient in custom analog/digital/RF cell layout as a top-level lead.
Strong expertise in floor planning, top-down layouts, area optimization, and managing critical devices.
Demonstrated experience in minimizing parasitic issues and creating high-quality layouts for Analog and Mixed Signal (AMS) designs in Cadence Virtuoso XL/GXL.
Proficiency in layout noise-coupling suppression techniques and isolating critical analog blocks.
Skilled in addressing EM/IR issues, preventing latch-up, mitigating ESD, and ensuring component and signal path matching.
High attention to detail with the ability to deliver optimized layouts efficiently.
Advantageous Qualifications
Knowledge of semiconductor device physics, process development, and analog/mixed signal IC design and testing.
Experience with SKILL, Perl, C-Shell, and/or Python scripting to enhance layout productivity.
Proficiency in Cadence Virtuoso’s advanced features, including GXL, EAD, and Constraint Manager.
Familiarity with deep submicron CMOS circuits, finFETs, and dual patterning.
Technical understanding of IR drop, RC delay, electro-migration, self-heating, and coupling capacitance.
Requirement: Proficiency in Cadence Virtuoso and Cadence Layout XL.
Pay Details: $47.79 to $60.51 per hour
Benefit offerings available for our associates include medical, dental, vision, life insurance, short-term disability, additional voluntary benefits, EAP program, commuter benefits and a 401K plan. Our benefit offerings provide employees the flexibility to choose the type of coverage that meets their individual needs. In addition, our associates may be eligible for paid leave including Paid Sick Leave or any other paid leave required by Federal, State, or local law, as well as Holiday pay where applicable.
Equal Opportunity Employer/Veterans/Disabled
To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to https://www.pdstech.com/candidate-privacy
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
- The California Fair Chance Act
- Los Angeles City Fair Chance Ordinance
- Los Angeles County Fair Chance Ordinance for Employers
- San Francisco Fair Chance Ordinance
